An integrated circuit (IC) chip may include one or more memory arrays used to store data. The one or more memory arrays may be grouped in one or more sets. To test such a chip, an ABIST test may be performed on the IC chip (e.g., to determine whether the IC chip includes any defects). During an ABIST test, a pattern of data is provided to the IC chip and written into one or more of the memory arrays (e.g., each memory array in a set of memory arrays). The data then is read out of the one or more memory arrays and compared to the data written into the one or more memory arrays. The resulting information is used to determine whether a failure occurred in one or more of the memory arrays.
An IC chip may include additional circuitry for performing an ABIST test. In one conventional testing configuration, a different latch (e.g., an observation latch) is coupled to each memory array for storing data that is read from the memory array. In this manner, the pattern of data written into a memory array may be read out of the memory array and stored in the observation latch associated with the memory array.
Because each observation latch occupies a large amount of space on an IC chip, including an observation latch for each memory array of the IC chip consumes a sizeable amount of real estate or floor plan area of the IC chip. Accordingly, methods and apparatus for testing integrated circuits that consume less chip real estate would be desirable